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Referencias Bibliográficas

R .D. Acosta, J. Kjelstrup, and H. C. Torng, "An Instruction Issuing Approach To Enhancing Performance in Multiple Functional Unit Processors", IEEE Trans. Computers, pp. 815-825. Sept. 1986.

A. Agarwal, B. H. Lim, D. Kranz, and J. Kubiatowicz, "April: A Processor Arquitecture for Multiprocessing", Proc. 15th Annual Int. Symp. Computer Arch., pp. 104 - 114 . 1990.

DEC, "Alpha Architecture Handbook," Digital Equipment Corporation, BoxBoro, MA, 1992.

G. M Amdahl, "Validity of Single Processor Approach to Achieving Large Scale Computing Capability," Proc. ADIPS Conf., pp. 483-485, Reston, VA., 1967.

K. E. Batcher, "Design of a Massively Parallel Processor," IEEE Trans. Computers, pp. 836-840, Sept. 1980.

A. J. Bernstein, "Analysis of Programs For Parallel Processing," IEEE Trans. Computers, pp. 746-757, Oct. 1966.

S. Brawer, Introduction To Parallel Programming, Academic Press, New York. 1989.

J. Cocke and V. Markstein, "The Evolution of RISC Technology at IBM," IBM J. Res. and Develop., 34 (1): 4-11, 1990.

H. G. Cragon, Branch Strategy Taxonomy and Performance Models, IEEE Computers Society Press, Los Alamitos, CA, 1992.

Cray, Cray-1 Computer System Hardware Reference Manual, Cray Research Institute, 1977.

G. Cybenko and D. J. Kuck, "Revolution or Evolution," IEEE Spectrum, 29(9):39-41, 1992.

S. Dasgupta. Computer Architecture. A Modern Synthesis Vol. 1 and Vol. 2. John Wiley & Sons. 1989.

P. G. Emma and E. S. Davidson, "Characterization of Branch and Data Dependences in Programs for Evaluating Pipeline Performance," IEEE Trans. Computers, 36:859-875, 1987.

G. P. Monzón, "Arquitectura y Organización del Computador". Senda. 1993.

A. J. Van de Goor, Computer Architecture and Design, Addison-Wesley. 1989.

T. R. Gross, "Code Optimization Techniques For Pipelined Architectures," Proc. IEEE Computer Society Spring Int. Conf., pp. 278-285, 1983.

J. L Hennessy and D. A. Patterson, Computer Architecture, A Quantitative Approach, Morgan Kaufmann, San Mateo California.

K. Hwang. Advanced Computer Architecture, Programmability, Scalability and Parallelism. McGraw Hill Computer Series 1994.

N. P. Jouppi and D. W. Wall, "Available Instruction Level Parallelism for Superescalar and Superpipeline Machines," Proc. Third Int. Conf. Arch. Support for Prog. Lang. and OS, pp. 272-282, ACM Press, New York, 1989.

P.M Kogge, The Architecture of Pipeline Computers, McGraw Hill, 1981.

J. K Lee and A. Smith, "Branch Prediction Strategies and Branch Target Buffer Design," IEEE Computer, 17(1):6-22, 1984.

G. S. Sohi, "Instruction Issue Logic For High Performance, Interruptible, Multiple Functional Unit, Pipeline Computers," IEEE Trans. Computers, 2nd ed., IEEE Trans Computers, 39(3):349-359, March 1990.

W. Stalings. Reduced Instruction Set Computers, 2nd ed., IEEE Computer Society Press, Los Alamitos, CA, 1990.

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